GATE Communication system MCQ’s
1) The convergence of Fourier transform is
a) along jw axis in splane
b) on a rectangular strip in splane
c) along a circle in splane
d) on a circular strip in splane
2) Convolution of two voltage pulses of amplitude 2 Volt and width 2 sec is a
a) Rectangular pulse
b) square pulse
c) Trapezoidal
d) Triangular pulse
3) The FT of v(t) is for w<=1. The Energy dissipated by 1 resistor, if v(t) is applied to it is
a) 1/
b) 2/
c)
d)
4) equals
a)2
b) 2 u(t)
c)
d) 0.5
5) A box contains 12 balls numbered from 1 to 12. If a ball is taken at random, what is the probability of getting a ball with a number which is a multiple of either 2 or 3.
______________
6) A box contains 2000 transistors of which 5 % are defective. A second box contains 500 transistors of which 40% are defective. Two other boxes contain 1000 transistors of which 10% are defective transistors. A single transistor is taken at random from one of the boxes.
i) What is the probability that selected transistor is defective?
ii) What is the probability that defective transistor is taken from box 2?
__________
……………………………………
Post your answers in the comment section
1a 2d 4d
6 – Use Baye’s theorem
GATE 2017 Feedback Amplifier practice questions
1) When negative feedback is introduced in a voltage amplifier, the lower cutoff frequency
a) Changes by a factor AB
b) Decreases by a factor 1+AB
c) Increases by a factor 1+AB
d) Decreases by a factor A/(1+AB)
2) Negative feedback in voltage series Amplifier
a) Increases input impedance and decreases output impedance
b) Decreases input impedance and decreases output impedance
c) Decreases input impedance and increases output impedance
d) Increases input impedance and increases output impedance
3) Emitter follower is a
a) Current series feedback amplifier
b) Voltage series feedback amplifier
c) Current shunt feedback Amplifier
d) Voltage shunt feedback amplifier
4) Which of the following parameters won’t get affected by feedback?
a) Gain
b) Bandwidth
c) Gain Bandwidth product
d) None of these
5) Effect of feedback on output Offset voltage of an OPAMPS
a) Increases
b) decreases
c) Remains same
d) None of these
Working of BICMOS NAND GATE
There are many logical families such as RTL, DTL, ECL, CMOS etc.
All have their advantages and disadvantages. However, in the past decade, CMOS is ruling the electronics field because of its SIZE and POWER.
CMOS(Complementary metal oxide semiconductor) has ZERO static power dissipation. However, The switching speed of CMOS is very low compared to BJT, and also CMOS cannot drive large current to the load. In order to drive large current to the load, the size of MOS needs to be significantly increased.
In order to incorporate the advantages of both CMOS and BJT, new logical family came into existence and that logical family is called BICMOS. In this post we will see the working of BICMOS NAND GATE and appreciate the work.
This is the two input BICMOS NAND gate.
It consists of
1) 2 PMOS PA and PB
2) 4 NMOS, NA1, NB1, NA3, NB3
3) Two BJT’s QP and Q0
NAND GATE
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
Purpose of Various devices
 PA, PB, NA1 and NB1 are used for logical purposes(Just like in CMOS)
 N2, NB3 and NA3 are used to remove base charge from the transistors.
Why to remove the base charge anyway?
 For high switching speeds of the BJT’s, we need to remove the base charge from the transistor. In order to remove the charge from the base of the transistor we need a mechanism, that can be achieved by using these 3 NMOS.
 If we do not remove the base charge, the transistor will be in ON state and takes a lot of time to go to the OFF state. If we do not remove the base charge, the half purpose of BICMOS will be lost.
Case 1 : Both A and B are low.
If both the inputs VA and VB(Refer the circuit) are low(0). PA and PB will be ON and the base of QP will be high. Thus the top BJT(Q) will be ON which pulls the output UP . If there is a capacitive load. The output current will be almost 101 times the base current i.e it will be 101*IB(Assuming beta of transistor is 100). (if there was no BJT, the output current would be just IB).
Also, note that N2 is getting input from the base of QA transistor. Since the base of QP is HIGH(say 5v), it will turn on N2 . Since N2 is ON, it will PULL THE BASE CHARGE OUT OF Q0 transistor. So, if both the inputs are low, QP is ON and Q0 is OFF. It is very important to appreciate the role of N2 here which facilitates high switching speed.
Case 2 :Both A and B are high
NB3 and NA3 NMOS make sure that QP is in OFF state. PA and PB are OFF. NB1, NA1 will be ON. The output is discharged via NB1, NA1 and Q0(High Speed). N2 will be effectively out of circuit in this case. So, Q0 is ON and QP is OFF.
I have discussed the 2 cases. You can correlate with the other 2 inputs.
Disadvantages of BICMOS
1) Fabrication cost is high
2) Due to VBE(Base to emitter voltage, 0.7v approximately) of BJT’s , desirable performance is not obtained when the BICMOS gates are operated at lesser voltages (3V, 2.4V) etc.
GATE syllabus for ECE 2017
EC Electronics and Communications
Section 1: Engineering Mathematics
Linear Algebra: Vector space, basis, linear dependence and independence, matrix
algebra, eigen values and eigen vectors, rank, solution of linear equations – existence
and uniqueness.
Calculus: Mean value theorems, theorems of integral calculus, evaluation of definite and
improper integrals, partial derivatives, maxima and minima, multiple integrals, line, surface
and volume integrals, Taylor series.
Differential Equations: First order equations (linear and nonlinear), higher order linear
differential equations, Cauchy’s and Euler’s equations, methods of solution using variation
of parameters, complementary function and particular integral, partial differential
equations, variable separable method, initial and boundary value problems.
Vector Analysis: Vectors in plane and space, vector operations, gradient, divergence and
curl, Gauss’s, Green’s and Stoke’s theorems.
Complex Analysis: Analytic functions, Cauchy’s integral theorem, Cauchy’s integral
formula; Taylor’s and Laurent’s series, residue theorem.
Numerical Methods: Solution of nonlinear equations, single and multistep methods for
differential equations, convergence criteria.
Probability and Statistics: Mean, median, mode and standard deviation; combinatorial
probability, probability distribution functions – binomial, Poisson, exponential and normal;
Joint and conditional probability; Correlation and regression analysis.
Section 2: Networks, Signals and Systems
Network solution methods: nodal and mesh analysis; Network theorems: superposition,
Thevenin and Norton’s, maximum power transfer; Wye‐Delta transformation; Steady state
sinusoidal analysis using phasors; Time domain analysis of simple linear circuits; Solution of
network equations using Laplace transform; Frequency domain analysis of RLC circuits;
Linear 2‐port network parameters: driving point and transfer functions; State equations for
networks.
Continuoustime signals: Fourier series and Fourier transform representations, sampling
theorem and applications; Discretetime signals: discretetime Fourier transform (DTFT),
DFT, FFT, Ztransform, interpolation of discretetime signals; LTI systems: definition and
properties, causality, stability, impulse response, convolution, poles and zeros, parallel and
cascade structure, frequency response, group delay, phase delay, digital filter design
techniques.
Section 3: Electronic Devices
Energy bands in intrinsic and extrinsic silicon; Carrier transport: diffusion current, drift
current, mobility and resistivity; Generation and recombination of carriers; Poisson and
continuity equations; PN junction, Zener diode, BJT, MOS capacitor, MOSFET, LED, photo
diode and solar cell; Integrated circuit fabrication process: oxidation, diffusion, ion
implantation, photolithography and twintub CMOS process.
Section 4: Analog Circuits
Small signal equivalent circuits of diodes, BJTs and MOSFETs; Simple diode circuits:
clipping, clamping and rectifiers; Singlestage BJT and MOSFET amplifiers: biasing, bias
stability, midfrequency small signal analysis and frequency response; BJT and MOSFET
amplifiers: multistage, differential, feedback, power and operational; Simple opamp
circuits; Active filters; Sinusoidal oscillators: criterion for oscillation, singletransistor and opamp
configurations; Function generators, waveshaping circuits and 555 timers; Voltage
reference circuits; Power supplies: ripple removal and regulation.
Section 5: Digital Circuits
Number systems; Combinatorial circuits: Boolean algebra, minimization of functions using
Boolean identities and Karnaugh map, logic gates and their static CMOS
implementations, arithmetic circuits, code converters, multiplexers, decoders and PLAs;
Sequential circuits: latches and flip‐flops, counters, shift‐registers and finite state machines;
Data converters: sample and hold circuits, ADCs and DACs; Semiconductor memories:
ROM, SRAM, DRAM; 8bit microprocessor (8085): architecture, programming, memory and
I/O interfacing.
Section 6: Control Systems
Basic control system components; Feedback principle; Transfer function; Block diagram
representation; Signal flow graph; Transient and steadystate analysis of LTI systems;
Frequency response; RouthHurwitz and Nyquist stability criteria; Bode and rootlocus plots;
Lag, lead and laglead compensation; State variable model and solution of state
equation of LTI systems.
Section 7: Communications
Random processes: autocorrelation and power spectral density, properties of white noise,
filtering of random signals through LTI systems; Analog communications: amplitude
modulation and demodulation, angle modulation and demodulation, spectra of AM and
FM, superheterodyne receivers, circuits for analog communications; Information theory:
entropy, mutual information and channel capacity theorem; Digital communications:
PCM, DPCM, digital modulation schemes, amplitude, phase and frequency shift keying
(ASK, PSK, FSK), QAM, MAP and ML decoding, matched filter receiver, calculation of
bandwidth, SNR and BER for digital modulation; Fundamentals of error correction,
Hamming codes; Timing and frequency synchronization, intersymbol interference and its
mitigation; Basics of TDMA, FDMA and CDMA.
Section 8: Electromagnetics
Electrostatics; Maxwell’s equations: differential and integral forms and their interpretation,
boundary conditions, wave equation, Poynting vector; Plane waves and properties:
reflection and refraction, polarization, phase and group velocity, propagation through
various media, skin depth; Transmission lines: equations, characteristic impedance,
impedance matching, impedance transformation, Sparameters, Smith chart;
Waveguides: modes, boundary conditions, cutoff frequencies, dispersion relations;
Antennas: antenna types, radiation pattern, gain and directivity, return loss, antenna
arrays; Basics of radar; Light propagation in optical fibers.
GATE VLSI Questions and answers
1) Why Silicon is preferred over Germanium in semiconductor devices?
– The major raw material for Si wafer fabrication is sand which is widely present in the nature.
– SiO2 which is a very good insulator can be easily processed. This layer of oxide is used for the gate oxide in MOSFET
Temperature stability of silicon is good, it can withstand in temperature range typically 140C to 180C whereas Germanium is much temperature sensitive only up to 70C.
2) What is the difference between dry oxidation and wet oxidation and which is purest among these two?

Dry Oxidation
Si + O2 > SiO2
This growth is relatively slow.But this process yields high quality oxide layers.

Wet Oxidation
Si +2H20 –> SiO2 + 2H2 ( Fast growth, less pure)
3) Effect of Body effect on Threshold Voltage if vsB > 0
Ans : We note that the voltage vSB (voltage sourcetobody) is not
necessarily equal to zero (i.e., vSB > 0), which means that this voltage vSB will attract some electrons from the substrate (In Case of P Substrate), thus more voltage is needed to create the channel(SO THRESHOLD VOLTAGE INCREASES).
4) In MOSFET, the polarity of the inversion layer is same as that of (GATE 1989)
a) Charge on the gate electrode
b) Minority carriers in the drain
c) Majority carriers in the substrate
d) Majority carriers in the source
Ans : d
5) In an nMOSFET, the susbstrate is
a) Heavily doped p type
b) lightly doped p type
c) heavily doped n type
d) lightly doped n type
Ans : a
( Why P+ is used ahead of P, post your observations in comment section)
6) Vt of nMOSFET is 0.5V. It is biased with = 3V, , then the MOSFET is in
a) Cutoff
b) Saturation
c) Linear
d) Inverse Saturatiom
What to expect from GATE ECE 2017 which is conducted by IIT Roorkee?
As GATE 2017 is hardly 45 months away, every aspiring student across the country will have one question in the mind. “What to expect from GATE ECE 2017 which is conducted by IIT Roorkee?”
Even though GATE examination papers will be formed by a committee consisting of faculty from all over the India. After years of analyzing, one can say that some IIT’s are known for some branches and one can expect “Really good questions”(WE mean TOUGH) in that particular GATE paper than the other branch paper. Keeping that in mind one can predict the difficulty of GATE paper off the top of one’s head.
This year, GATE examination will be conducted by IIT Roorkee and here are some important dates which are already published.
IIT Roorkee is very famous for Civil Engineering so one can expect some interesting questions in that dept. However, we from a family of Electronics and communication can breath a sigh of relief for sometime. IIT Roorkee previously conducted the GATE examination in the year 2009. And if we analyze the difficulty of EC paper in the year 2009, it was relatively easy. So, we may expect a moderate ECE paper this year.
Any GATE paper will be formed in such a way that it will test student’s understanding of basic concepts, logic, numerical ability, aptitude and some questions will be twisted to test one’s deep understanding of the subject.
Emphasis on any of above aspects will purely depend on the committee formed during that academic year.
Though one cannot predict 100% that the GATE exam will be easy, moderate or difficult, some old school tricks will help you to excel.
– Solving previous examination questions of last 15 years.
– Concentrating on Important topics and studying based on mark distribution which will be put up on website(http://www.iitr.ac.in)
All the best for your GATE preparation
Regards
gateece.org
GATE Electromagnetic question and solution
In this post, we will see how to approach an electromagnetics question which had appeared in GATE 1995 for 2 marks.
Soln: First, let’s understand the question and draw a rough figure based on the question
As you see, the current direction is towards Z axis. Now the first question is to find out the direction of Magnetic field.
Can the Magnetic field exist in Z direction – No because Magnetic field is perpendicular to the direction of current.
Can the Magnetic field exist in Y direction? Let’s analyse that. Just take two current lines flowing from a plane Y=0, in this case, current is coming out of OUR computer screen, so according to right hand rule, the magnetic field will be in the anticlockwise direction.
As you can see the magnetic field at the point due to the 2 current lines is only towards x direction, thus magnetic field due to infinite current lines contributes only in x direction and all the y components will be cancelled out.
Now In order to calculate the magnetic field due to the uniform current flowing in the Y=0 plane, we need to consider the small portion of the surface and draw appropriate ‘Amperian loop’ enclosing the current and apply Ampere’s law. In this case the amperian loop will be a rectangular box which is parallel to XY plane and extending an equal distance above and below the surface as shown in the above figure(1).
Applying Ampere’s law
= 2Bl== where K= Current/metre
So in this case
B=
H= K/2 where K=30 mA/m
So the correct Answer is H= 15 mA/m